Abstract :- Spurious-Power Suppression Technique for Multimedia/DSP
Applications:- :-
This paper presents the
design exploration and applications of a spurious-power suppression technique
(SPST) which can dramatically reduce the power dissipation of combinational
VLSI designs for multimedia/DSP purposes. The proposed SPST separates the
target designs into two parts, i.e., the most significant part and least
significant part (MSP and LSP), and turns off the MSP when it does not affect
the computation results to save power. Furthermore, this paper proposes an
original glitch-diminishing technique to filter out useless switching power by
asserting the data signals after the data transient period.
There are different entities
that one would like to optimize when designing a VLSI circuit. These entities
can often not be optimized
simultaneously, only improve one entity at the expense of one or more others
The design of an efficient integrated circuit in terms of power, area, and
speed simultaneously, has become a very challenging problem. Power dissipation is
recognized as a critical parameter in modern the objective of a good multiplier
is to provide a physically compact, good speed and low power consuming chip. To
save significant power consumption of a VLSI design, it is a good direction to
reduce its dynamic power that is the major part of total power dissipation. In
this paper, we propose a high speed low-power multiplier adopting the new SPST
implementing approach. This multiplier is designed by equipping the Spurious
Power Suppression Technique (SPST) on a modified Booth encoder which is
controlled by a detection unit using an AND gate. The modified booth encoder
will reduce the number of partial products generated by a factor of 2. The SPST
adder will avoid the unwanted addition and thus minimize the switching power
dissipation.
In
this project we used Modelsim for logical verification, and further
synthesizing it on Xilinx-ISE tool using target technology and performing
placing & routing operation for system verification on targeted FPGA.
Advantages
- Finite impulse response filters,
- Fast Fourier transforms,
- Discrete cosine transforms,
- Convolution, and other important DSP and multimedia kernels.
Language Used
- Verilog HDL
Tools Required
- MODELSIM – Simulation
- XILINX-ISE – Synthesis
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